A power device performs a central role as a switching element of a power conversion device, such as an inverter or a converter. Even among power devices, an insulated gate bipolar transistor (IGBT) in particular has good gate controllability, and can achieve low on-voltage using a conductivity modulation effect. Therefore, the IGBT is widely used in various voltage regions. A planar gate IGBT is mainly used in a breakdown voltage class of 3,300 V or more. A planar gate IGBT includes a gate electrode on a surface of a semiconductor substrate. Meanwhile, the application of a trench gate structure IGBT is predominant in a breakdown voltage class of 1,700 V or less. In a trench gate structure IGBT, a gate electrode is embedded across an oxide film in a groove (trench) formed in a surface of a semiconductor substrate.
A trench gate structure can have a finer cell structure than a planar gate structure. Also, a trench gate structure does not have a JFET region (a region sandwiched by adjacent p-base regions, which is a portion in which current concentrates) unique to a planar gate structure. Therefore, it is possible to reduce the on-voltage further in a trench gate structure than in a planar gate structure. Also, when the IGBT is in an on-condition, the greater part of an on-voltage drop, which leads to conduction loss, is a voltage drop in a drift region. Because of this, strengthening a so-called injection enhancement (IE) effect, wherein carriers (electrons and holes) are confined as far as possible in the drift region, also leads to low on-voltage. As a surface structure having the IE effect, there is, for example, an IEGT (injection enhanced gate transistor) structure, wherein one portion of an inversion layer channel is inactive, and holes are amassed in the drift region in the vicinity of the channel portion (for example, refer to Patent Document 1). Also, there is a microcell structure IGBT, wherein a p-base layer is partially formed in a silicon mesa portion sandwiched by trench side walls (for example, refer to Patent Document 2).
FIG. 20 shows a plan layout diagram of a microcell structure IGBT described in Patent Document 2. A gate insulating film, an interlayer insulating film, an emitter electrode, and a passivation film are omitted from FIG. 20. FIG. 21 shows a sectional view along a section line A-A′ in FIG. 20. The section line A-A′ intersects a trench and an emitter cell. In the specification and attached drawings, a layer or region being prefixed by n or p means that a large number of electrons or positive holes respectively are carriers. Also, + or − appended to n or p means that there is a higher impurity concentration or lower impurity concentration than in a layer or region to which + or − is not appended.
As shown in FIG. 20 and FIG. 21, a trench 1 is formed in a stripe form. A gate electrode 2 is embedded across a gate insulating film 3 in the trench 1. An emitter cell 7 including a p-base region 4, an n+ emitter region 5, and a p+ region 6 is disposed at every predetermined interval W in a mesa portion between neighboring trenches 1. The emitter cell 7 is disposed alternately, leaving a predetermined distance L, in the mesa portion on either side of one trench 1. In each emitter cell 7, an emitter electrode 10 is electrically connected to the n+ emitter region 5 and p+ region 6 across a contact region 9 that penetrates an interlayer insulating film 8. The emitter electrode 10 and gate electrode 2 are isolated by the interlayer insulating film 8. A passivation film 11 is provided on the emitter electrode 10. An n-buffer layer 13, a p-collector layer 14, and a collector electrode 15 are provided on a main surface of the n− layer 12 on the side opposite a main surface on the emitter cell 7 side. In FIG. 20, a region bounded by a two-dot chain line indicates an active portion unit cell 16. The dimension of the active portion unit cell 16 in the longitudinal direction of the trench 1 is W/2.
Also, there is known a so-called carrier stored trench-gate bipolar transistor (CSTBT). A CSTBT includes an n-layer in the vicinity of the channel with an impurity concentration higher than that of the drift region. Because of this, holes accumulate in the drift region (for example, refer to Patent Document 3). Also, there is known a structure wherein, in order to suppress an electric field in the vicinity of the n-layer in the vicinity of the channel, one portion of a trench gate is short circuited with the emitter. Also, there is known a wide-pitch structure wherein, in order to increase short circuit capability, saturation current is reduced by lengthening the trench pitch in one portion (for example, refer to Patent Document 4). In this way, the channel density of the trench IGBT is lower, in principle or in design, than a channel density that can be provided in a trench side surface.
Meanwhile, the manufacturing process of a trench gate structure is more complicated than the manufacturing process of a planar gate structure. Because of this, when comparing chip cost in a trench gate IGBT and planar gate IGBT, the cost in the trench gate IGBT is higher. Consequently, in order to provide a switching device with still higher added value at a low cost, it is necessary to consider a device structure that can be manufactured more simply, while maintaining IGBT performance. As one example thereof, there is known a structure of an IGBT that includes a planar gate and a trench gate (for example, refer to Patent Document 5).
FIG. 22 shows a sectional view of an IGBT described in Patent Document 5. As shown in FIG. 22, the n+ emitter region 5 is formed distanced from the trench 1 in the p-base region 4. The gate insulating film 3 and gate electrode 2 are provided on a surface of the p-base region 4 between the n+ emitter region 5 and trench 1, along a side wall and bottom surface of the trench 1, overlapping one portion of the n+ emitter region 5. Consequently, an inversion layer channel is formed along a trench side wall portion of the p-base region 4 and a substrate surface of a planar gate portion. A structure similar to the device structure shown in FIG. 22 is also disclosed in another patent application (for example, refer to Patent Document 6 and Patent Document 7).